1. Field of the Invention
The present invention relates to the manufacturing of a mirror device (also known as a “digital micromirror device” or “micromirror device”) provided for a projection device and particularly to a method for manufacturing a mirror device by means of a plurality of sacrificial layers.
2. Description of the Related Arts
Even though there have been significant advances made in recent years in the technology of implementing electromechanical micromirror devices as spatial light modulators (SLM), there are still limitations and difficulties when these are employed to display high quality images. Specifically, when the display images are digitally controlled, the quality of the images is adversely affected because the images are not displayed with a sufficient number of gray scale gradations.
Electromechanical mirror devices are drawing a considerable amount of interest as spatial light modulators (SLM). The electromechanical mirror device consists of a mirror array arranging a large number of mirror elements. In general, the number of mirror elements range from 60,000 to several millions and are arranged on the surface of a substrate in an electromechanical mirror device.
Refer to FIG. 1A for a digital video system 1 as disclosed in relevant U.S. Pat. No. 5,214,420, which includes a display screen 2. A light source 10 is used to generate light energy to illuminate display screen 2. Light 9 is further concentrated and directed toward lens 12 by mirror 11. Lens 12, 13, and 14 serve a combined function as a beam columnator to direct light 9 into a column of light 8. A spatial light modulator 15 is controlled by a computer through data transmitted over data cable 18 to selectively redirect a portion of the light from path 7 toward lens 5 to display on screen 2. The SLM 15 has a surface 16 that includes switchable reflective elements, e.g., micro-mirror devices 32 with elements 17, 27, 37, and 47 as reflective elements attached to a hinge 30, as shown in FIG. 1B. When element 17 is in one position, a portion of the light from path 7 is redirected along path 6 to lens 5 where it is enlarged or spread along path 4 to impinge the display screen 2 so as to form an illuminated pixel 3. When element 17 is in another position, light is not redirected toward display screen 2 and hence pixel 3 would be dark.
Each of the mirror elements constituting a mirror device functions as a spatial light modulator (SLM), and each mirror element comprises a mirror and electrodes. A voltage applied to the electrode(s) generates a Coulomb force between the mirror and the electrode(s), making it possible to control and incline the mirror. The inclined mirror is “deflected” according to a common term used in this patent application for describing the operational condition of a mirror element.
When a mirror is deflected with a voltage applied to the electrode(s), the deflected mirror also changes the direction of the reflected light in reflecting an incident light. The direction of the reflected light is changed in accordance with the deflection angle of the mirror. The present patent application refers to the light reflected to a projection path designated for image display as “ON light”, and refers to a light reflected in a direction away from the designated projection path for image display as “OFF light”. When only a portion of the reflected light is directed in the ON light direction and the light reflected by the mirror to the projection path is of lesser intensity than the “ON light”, it is referred to as “intermediate light”.
The present patent application defines an angle of rotation along a clockwise (CW) direction as a positive (+) angle and that of a counterclockwise (CCW) direction as a negative (−) angle. A deflection angle is defined as zero degrees (0°) when the mirror is in the initial state.
The on-and-off states of a micromirror control scheme, such as that implemented in the U.S. Pat. No. 5,214,420 and by most conventional display systems, limit image display quality. This is because the application of a conventional control circuit limits the gray scale (PWM between ON and OFF states) by the LSB (least significant bit, or the least pulse width). Due to the ON-OFF states implemented in conventional systems, there is no way to provide a pulse width shorter than the LSB. The least brightness, which determines the gray scale, is the light reflected during the least pulse width. A limited gray scale leads to lower image quality.
In FIG. 1C, a circuit diagram of a control circuit for a micro-mirror according to U.S. Pat. No. 5,285,407 is presented. The control circuit includes memory cell 32. Various transistors are referred to as “M*” where * designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5, and M7 are p-channel transistors; transistors, M6, M8, and M9 are n-channel transistors. The capacitances, C1 and C2, represent the capacitive loads presented to memory cell 32. Memory cell 32 includes an access switch transistor M9 and a latch 32a, which is the basis of the Static Random Access switch Memory (SRAM) design. All access transistors M9 in a row receive a DATA signal from a different bit-line 31a. The particular memory cell 32 to be written is accessed by turning on the appropriate row select transistor M9, using the ROW signal functioning as a word-line. Latch 32a is formed from two cross-coupled inverters, M5/M6 and M7/M8, which permit two stable states. State 1 is Node A high and Node B low and state 2 is Node A low and Node B high.
The mirror is driven by a voltage applied to the landing electrode and is held at a predetermined deflection angle on the landing electrode. An elastic “landing chip” is formed on the portion of the landing electrode that comes into contact with the mirror, and assists in deflecting the mirror towards the opposite direction when the deflection of the mirror is switched. The landing chip is designed to have the same potential as the landing electrode so that a shorting is prevented when the landing electrode is in contact with the mirror.
Each mirror formed on a device substrate has a square or rectangular shape, and each side has a length of 4 to 15 um. In this configuration, a portion of the reflected light is reflected not from the mirror surface but from the gaps between the mirrors or other surfaces of the mirror device. These “unintentional” reflections are not applied to project an image and are inadvertently generated. The contrast of the displayed image is degraded due to the interference from these unintentional reflections generated by the gaps between the mirrors. In order to overcome this problem, the mirrors are arranged on a semiconductor wafer substrate with a layout to minimize the gaps between the mirrors. One mirror device is generally designed to include an appropriate number of mirror elements, wherein each mirror element is manufactured as a deflectable mirror on the substrate for displaying a pixel of an image. The appropriate number of elements for displaying an image is configured in compliance with the display resolution standard according to the VESA Standard defined by the Video Electronics Standards Association or by television broadcast standards. When a mirror device is configured with the number of mirror elements in compliance with WXGA (resolution: 1280 by 768) defined by VESA, the pitch between the mirrors of the mirror device is 10 μm, and the diagonal length of the mirror array is about 0.6 inches.
The control circuit, as illustrated in FIG. 1C, controls the mirrors to switch between two states, and the control circuit drives the mirror to oscillate to either an ON or OFF deflected angle (or position) as shown in FIG. 1A.
The minimum intensity of light reflected from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally-controlled image display apparatus, is determined by the least length of time that the mirror may be controlled to stay in the ON position. The length of time a micromirror is in an ON position is controlled by a multiple bit word. FIG. 1D shows the “binary time intervals” when controlling micromirrors with a four-bit word. As shown in FIG. 1D, the time durations have relative values of 1, 2, 4, 8, which in turn define the relative brightness for each of the four bits, where “1” is the least significant bit and “8” is the most significant bit. According to the control mechanism as shown, the minimum controllable differences between gray scales for showing different levels of brightness is a represented by the “least significant bit” that maintains the micromirror at an ON position.
For example, assuming n bits of gray scales, one time frame is divided into 2n−1 equal time periods. For a 16.7-millisecond frame period and n-bit intensity values, the time period is 16.7/(2n−1) milliseconds.
Having established these times for each pixel of each frame, pixel intensities are quantified such that black is a 0 time period, the intensity level represented by the LSB is 1 time period, and the maximum brightness is 2n−1 time periods. Each pixel's quantified intensity determines its ON-time during a time frame. Thus, during a time frame, each pixel with a quantified value of more than 0 is ON for the number of time periods that correspond to its intensity. The viewer's eye integrates the pixel brightness so that the image appears the same as if it were generated with analogous levels of light.
For controlling deflectable mirror devices, the PWM applies data to be formatted into “bit-planes”, with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has n bit-planes. Then, each bit-plane has a 0 or 1 value for each display element. According to the PWM control scheme as described in the preceding paragraphs, each bit-plane is separately loaded and the display elements are controlled on the basis of bit-plane values corresponding to the value of each bit within one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed for 1 time period.
When adjacent image pixels are shown with a great degree of difference in the gray scales, due to a very coarse scale of controllable gray scale, artifacts are shown between these adjacent image pixels. That leads to image degradations. The image degradations are especially pronounced in the bright areas of display, where there are “bigger gaps” between gray scales of adjacent image pixels. The artifacts are generated by technical limitations in that the digitally controlled display does not provide sufficient gray scales. Thus, in the bright areas of the display, the adjacent pixels are displayed with visible gaps of light intensities.
As the micromirrors are controlled to have a fully on and fully off position, the light intensity is determined by the length of time the micromirror is at the fully on position. In order to increase the number of gray scales of a display, the speed of the micromirror must be increased such that the digital control signals can be increased to a higher number of bits. However, when the speed of the micromirrors is increased, a stronger hinge is necessary for the micromirror to sustain the required number of operational cycles for a designated lifetime of operation, In order to drive micromirrors supported on a stronger hinge, a higher voltage is required. In this case, the voltage may exceed twenty volts and may even be as high as thirty volts. Micromirrors manufactured by applying the CMOS technologies would probably not be suitable for operation at this higher range of voltages, and therefore, DMOS micromirror devices may be required. In order to achieve a higher degree of gray scale control, more complicated manufacturing processes and larger device areas are necessary when DMOS micromirrors are implemented. Conventional modes of micromirror control are therefore facing a technical challenge in that the gray scale accuracy has to be sacrificed for the benefits of a smaller and more cost effective image display system, due to the operational voltage limitations.
There are many patents related to light intensity control. These Patents include U.S. Pat. Nos. 5,589,852, 6,232,963, 6,592,227, 6,648,476, and 6,819,064. There are further patents and patent applications related to different shapes of light sources. These Patents includes U.S. Pat. Nos. 5,442,414 and 6,036,318 and Application 20030147052. U.S. Pat. No. 6,746,123 discloses special polarized light sources for preventing light loss. However, these patents and patent application do not provide an effective solution to overcome the limitations caused by insufficient gray scales in the digitally controlled image display systems.
Furthermore, there are many patents related to spatial light modulation including U.S. Pat. Nos. 2,025,143, 2,682,010, 2,681,423, 4,087,810, 4,292,732, 4,405,209, 4,454,541, 4,592,628, 4,767,192, 4,842,396, 4,907,862, 5,214,420, 5,287,096, 5,506,597, and 5,489,952. However, these inventions have not addressed or provided direct resolution for a person of ordinary skill in the art to overcome the limitations and difficulties discussed above.
In order to address the above problems, US Patent Application 20050190429 discloses a method for controlling the deflection angle of the mirror to express higher gray scales of an image. In this disclosure, the intensity of light produced during the oscillation period of mirror is between 25% to 37% of the intensity of light produced when the mirror is held in the ON position continuously.
According to such a control, it is not necessary to drive the mirror at a high speed. Thus, it is possible to provide higher gray scales using a hinge, which supports the mirror, with a low elastic constant. Hence, it is possible reduce the voltage applied to the electrode.
FIGS. 3A and 3B are cross-sectional views, taken along line II-II, of the single mirror element of the mirror device 200 shown in FIG. 2. The operation of the single mirror element 300 will be described below.
The single mirror element 300 comprises a mirror 302, an elastic hinge 304 for supporting the mirror, address electrodes 307a and 307b, and two memory cells, a first and second memory cell, for applying voltage to the address electrodes 307a and 307b such that the mirror 302 is controlled to be in a desired deflection state. A drive circuit and wiring (not shown) of each of the memory cells are usually provided inside the device substrate 303. The deflection direction of the mirror 302 can be controlled by controlling each of the memory cells with the signal of image data. Incident light can be modulated and reflected by the mirror 302 in its various deflection states.
FIG. 3A is a cross-sectional view of the mirror element 300 deflecting the mirror 302 to reflect incident light towards a projection optical system.
By supplying the memory cell with a signal (0, 1), a voltage of 0 [V] is applied to the address electrode 307a, and a voltage of Va [V] is applied to the address electrode 307b. As a result, the mirror 302 in the horizontal state is deflected by the Coulomb force in the direction of the address electrode 307b to which Va [V] is applied. This causes the mirror 302 to reflect incident light emitted from a light source 301 towards the projection optical system (ON light state). An insulating layer 306 is provided on the device substrate 303, and the hinge electrode 305 connected to the elastic hinge 304 is connected to the ground through a via-connector (not shown) provided on the insulating layer 306.
FIG. 3B is a cross-sectional view of the mirror element 300 deflecting the mirror 302 so as not to reflect incident light towards the projection optical system.
By supplying the memory cell with a signal (1, 0), voltage of Va [V] is applied to the address electrode 307a and voltage of 0 [V] is applied to the address electrode 307b. As a result, the mirror 302 in the horizontal state is deflected by the Coulomb force in the direction of the address electrode 307a to which Va [V] is applied. This causes incident light to be reflected in a direction other than the direction of a light path leading to the projection optical system (OFF light state).
FIGS. 4A through 4F are diagrams showing the outline of the manufacturing process of the mirror element 300 shown in FIGS. 3A and 3B above.
First, in FIG. 4A, an n-type or p-type impurity is infused to form a drive circuit, such as a transistor, into a semiconductor wafer substrate 303, in order to drive and control the mirror. Then, the hinge electrode 305 and address electrodes 307 (307a and 307b), connected to wiring (not shown) and the drive circuit, are formed on the semiconductor wafer substrate 303. An insulating layer 306 is formed on the semiconductor wafer substrate 303, the hinge electrode 305, and the address electrodes 307.
Next, in FIG. 4B, a sacrificial layer 401 is deposited on the insulating layer 306. The sacrificial layer 401 is used to maintain space between the undersurface of the mirror 302, formed in a later process, and the semiconductor wafer substrate 303. The thickness of the sacrificial layer 401 determines the height of the elastic hinge 304 supporting the mirror 302.
In FIGS. 4C and 4D, a portion of the sacrificial layer 401 is removed by etching, such that an opening is made. An elastic member to serve as the elastic hinge 304 is deposited in the opening. Additionally, the deposited elastic member is etched to obtain a desired shape for the elastic hinge. Then, the sacrificial layer 401 is polished until the surface of the elastic member is exposed.
In FIG. 4E, a mirror layer 402 is deposited in such a way that it is connected to the top surfaces of the sacrificial layer 401 and the elastic member 304.
In FIG. 4F, the mirror layer 402 is formed into the desired mirror shape by etching. Then, the entirety of the sacrificial layer 401 is removed by etching, in order to form the space in which a mirror can deflect. This completes the manufacturing process of a mirror element.
An inorganic-glass sacrificial layer can be formed using a method for depositing a material, such as SiH4 and O2, by means of a chemical vapor deposition (CVD) method or by using a coating method in which glass, such as solution layer PSG, is spin-coated. Since the inorganic-glass sacrificial layer formed with these methods has a hard surface, it can be polished. A mirror layer can be formed on the polished surface. The mirror layer is flat and almost uniform. However, in the process of removing a sacrificial layer, water is generated when the sacrificial layer is removed using vapor-phase hydrogen fluoride (HF) as an etchant. Water between the mirror 302 and the electrodes 307 may generate surface tension, intermolecular force, etc., causing the mirror 302 supported by the elastic member to deflect and adhere to the electrodes 307. In the manufacturing process, this phenomenon, known as stiction, can occur.
It is necessary for the mirror 302 and electrodes 307 to have conductivity. The mirror 302 is formed of a highly reflective material such as aluminum, gold, or silver. When the mirror 302 deflects towards the electrode 307, an electrical short occurs at the point of contact between the mirror 302 and electrode 307. In order to prevent the short from occurring, the insulating layer 306, composed of an oxidized compound, such as silicon dioxide (SiO2), covers and protects the surface of the electrode. However, since the insulating layer 306 has weak acid-resistance to hydrogen fluoride (HF) as an etchant, used in removing the sacrificial layer 401, the insulating layer 306 is also removed together with the sacrificial layer 401.
In addition, the insulating layer, acting as a protection film, is too thin at the base of the electrode 307. Therefore, when hydrogen fluoride (HF) is used as an etchant for removing the sacrificial layer, it easily penetrates to the inside of the semiconductor wafer substrate. This causes defects such as the removal of even silicon dioxide (SiO2), which is an insulating film inside the substrate.
The following are patent documents relate to the technology of manufacturing a conventional mirror device.
U.S. Pat. No. 6,906,845 discloses a technology of providing a mirror of a vertical hinge and a single sacrificial layer.
U.S. Pat. No. 6,753,037 discloses a technology of using organic material in a sacrificial layer.
U.S. Pat. No. 6,063,696 discloses a technology of using a photoresist layer on the top surface of a mirror.
U.S. Pat. No. 6,787,187 discloses a technology of coating the top surface of a mirror with a vapor phase.
U.S. Pat. No. 6,583,920 discloses a technology of providing a sacrificial layer composed of an organic material.
U.S. Pat. No. 5,936,760 discloses a method for manufacturing a vertical hinge and a mirror.
U.S. Pat. No. 7,138,693 discloses a technology of providing a barrier layer.
U.S. Pat. No. 6,686,291 discloses a process of releasing a sacrificial layer after it is placed on a package.
U.S. Pat. No. 5,817,569 discloses a technology of configuring a groove for dicing on a device between sacrificial layers.
U.S. Pat. No. 6,958,123 discloses a technology of removing a sacrificial layer composed of an organic material by means of supercritical liquid.
U.S. Pat. No. 6,849,471 discloses a technology of providing a barrier layer.
U.S. Pat. No. 6,960,305 discloses a technology of removing a sacrificial layer by means of a material containing halogen.
U.S. Pat. No. 5,425,845 discloses a difference between etching rates caused by different additives.
U.S. Pat. No. 6,815,361 discloses a technology of preventing stiction when removing a sacrificial layer under wet conditions.
U.S. Pat. No. 7,153,443 discloses a technology of providing a barrier layer.
US Patent Application Publication 2005/0206993 discloses a technology of providing a mirror layer and a hinge layer having a multilayer structure.